1. Field of the Invention
The invention relates to a transistor array for testing. Particularly, the invention relates to a method for reducing leakage current of a non-selected tested transistor in a transistor array for testing.
2. Description of Related Art
In order to learn electrical characteristics presented by circuit devices of various wafers, a designer generally disposes a plurality of test keys at a non-device area of the wafer, and obtains the electrical characteristics of the electronic devices of each region in the wafer by measuring the electrical characteristics of the test keys.
In a conventional technique domain, test keys of a so-called addressable transistor array are provided. The test keys formed by the transistor array can effectively use a limited space of the non-device area, and a maximum number of the transistors can be disposed thereto for measurement. Regarding the transistor array, any of the transistors can be tested through an addressing method by only configuring a common measurement pad, and configuration of an independent measurement pad for each of the transistors to be tested is unnecessary. In this way, the designer can obtain enough amounts of data through such transistor array without consuming a large wafer area.
However, in the transistor array of the conventional technique, the transistor that is not selected for testing may have a so-called sub-threshold leakage phenomenon, and since the number of the transistors that are not selected for testing is relatively large, a total leakage current may lead to an error testing result of the selected transistor.